Serial decimal adder utilizing magnetic core matrices

ABSTRACT

An electronic computer for the series-parallel processing of decimal numbers with the aid of decoder matrixes of ring cores coacting with an adder matrix of ring cores. Each of the matrixes is subdivided into two submatrixes of which at least one is inhibitable independently of the other. The half-select current wires of each matrix are linked with respective cores of both submatrixes. Each core in the decoder matrixes is linked with a different pair of such wires. The adder matrix has each core of only one of its submatrixes linked with a different pair of halfselect current wires. The cores of the other adder submatrix are twice linked with a single one of the respective wires.

United States Patent Inventor Horst Herger Bielefeld, Germany Appl. No. 624,645 Filed Mar. 1,1967 Patented Feb. I6, 1971 Assignee Anker-Werke Aktiengesellschaft Bieleleld, Germany Priority Apr. 28, 1966 Germany AS2292 SERIAL DECIMAL ADDER UTILIZING MAGNETIC CORE MATRICES Primary Examiner-Malcolm A. Morrison Assistant Examiner-David I-I. Malzahn AtrorneysCurt M. Avery, Arthur E. Wilfond, Herbert L.

Lerner and Daniel J. Tick ABSTRACT: An electronic computer for the series-parallel processing of decimal numbers with the aid of decoder matrixes of ring cores coacting with an adder matrix of ring cores. Each of the matrixes is subdivided into two submatrixes of which at least one is inhibitable independently of the other. The half-select current wires of each matrix are linked with respective cores of both submatrixes. Each core in the decoder matrixes is linked with a different pair of such wires. The adder matrix has each core of only one of its submatrixes linked with a different pair of half-select current wires. The cores of the other adder submatrix are twice linked with a single one of the respective wires.

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START SERIAL DECIMAL ADDER UTILIZING MAGNETIC CORE MATRICES My invention relates to an electronic computer for seriesparallel processing of decimal or other digital numbers.

Encoding devices, adding, multiplying and controlling systems have been equipped with ring-core matrix networks whose magnetizable memory cores are inductively linked with several signal windings. In Taschenbuch der Nachrichtenverarbeitung by K. Steinbuch, Edition of 1962, published by Springer-Verlag, there is described a single-place adding system composed of two submatrixes of which one furnishes the result when no transfer from the preceding decimal place occurs. The other submatrix furnishes the result in the event a transfer is to be taken into account. The proper selection of these submatrixes is effected by special control pulses. Also known is an electronic adding system composed of two ringcore matrixes (German Pat. 1,059,212) of which one upon occurrence of a digital sum requiring a decimal-place transfer controls a switching device which blocks the first ring-core matrix during addition of the digits appertaining to the next following decimal place, and which simultaneously controls a second ring-core matrix to perform this adding operation. The latter matrix furnishes a digital sum larger by the amount one than the digital sum of the two digits supplied.

The known electronic computers composed of ring-core matrixes are highly complicated on account of the large number of ring core required, which renders the accessory switching devices correspondingly voluminous so that the computers are extremely expensive to manufacture.

It is an object of our invention, relating to an electronic computer operating with core matrix networks for the seriesparallel processing of digital numbers, to considerably reduce the number of ring cores as well as the amount of associated circuitry.

Another, more specific object of the invention is to simplify the core matrixes and associated circuits in such computers by affording the half-select current wires, serving to write digit values into the individual cores of the matrixes, to be passed in two different directions through several ring cores coordinated to respectively different, predetermined digit values.

An electronic computer for the series-parallel processing of decimal numbers equipped with memory core matrix systems and designed according to the invention is characterized by the fact that the decoder matrixes into which the decimal numbers are to be written, as well as an adder matrix cooperating with the decoder matrixes, are each subdivided into two submatrixes, and that each of the data wires carrying the writing (half-select) current is inductively linked, preferably in two different directions, with given respective cores of both submatrixes.

According to a further preferred feature of the invention, the adder matrix of the electronic computer has each core of one submatrix linked to two different wires which carry the writing current for the decoded digits so that these cores are reversely magnetizable by two half-select currents coincidently flowing in the two wires, whereas the cores of the other submatrix are each linked twice with one and the same wire so as to be reversely magnetizable by the doubled halfselect current flowing through this wire.

According to another feature of the invention, the matrix for decoding decimal numbers to be written-in serially, simultaneously serves to effect the tens transfer of the decimal digit previously read out of the decoder matrix.

According to a further feature of the invention, the electronic computer is preferably provided with a decoder device which during addition -transfers the decoded values into the adder matrix under control by the programmer of the computer, and which during subtraction transfers in the same manner the nine-complements into the adder matrix.

The above-mentioned and further objects, advantages and features of the invention, said features being set forth with particularity in the claims annexed hereto, will be apparent from, and will be mentioned in, the following description of an embodiment of a computer according to the invention illustrated by way of example in the accompanying drawings. in

which:

FIG. 1 is a schematic circuit diagram of the entire computer.

FIG. 2 is a separate circuit diagram of a transfer decoder (CE) which forms part of the computer according to FIG. 1.

FIG. 3 is a separate circuit diagram of an adder matrix (DA) also appertaining to the computer of FIG. 1.

FIGS. 4, 5 and 6 show respectively, different circuit details of the same adder matrix.

FIG. 7 is a separate circuit diagram of an accumulator (AK) and of an appertaining selector network which form part of the computer shown in FIG. 1.

FIG. 8 is a circuit diagram of a complements decoder (KE). also with reference to FIG. 1.

- FIG. 9 is an explanatory table relating to the code employed in a particular embodiment described in this specification.

The electronic computer system shown in FIG. 1 comprises a two-way selector W, a transfer decoder CE, a complements decoder KE, an adder matrix DA, a code converter CW, an accumulator AK with a selector network AS, a driver stage T, a read-out amplifier LV, and a gate circuit To controllable by a switch S.

The two-way selector W is connected by wires a to f to a suitable input device (not illustrated) such as an accounting machine, a data memory device or with the input member or output member of some other logic system. (An accounting machine with data output terminals directly connectable to respective wires a to f in present FIG. 1 is illustrated and described in the copending application of G. Rethmeier and H. Berger, Ser. No. 621,724, filed Mar. 1, 1967, based on German application A 51 731 1Xc/42m of Mar. 3, 1966). The selector W is connected through leads 20a to 20f and through respective resistors 21a to 21f with the transfer decoder CE.

Located in the transfer decoder CE is a ring-core matrix 22 (FIGS. 1,2) composed of two submatrixes 23 and 24. The submatrix 23 comprises ring cores 23/0 to 23/9 and 23/A to 23/ E. The submatrix 24 comprises ring cores 24/1 to 24/10. The wire 20a extends in the x-direction through the ring cores 23/A, 23/B, 23/0, 23/1, 23/2 of submatrix 23 and also passes in the y-direction through the cores 24/3, 24/2 and 24]] of submatrix 24 to a bus conductor 26 connected to the collector 27 of a transistor 28. The emitter 29 of transistor 28 is connected to a conductor 30 which carries a voltage of U volt. The base 31 of transistor 28 is connected to a clockpulse line 32. The wire 20b extends in the x-direction through the ring cores 23/9, 23/3, 23/4, 23/5 and in the y-direction through the cores 24/6, 24/5, 24/4, 24/10, as well as through ring core 23/A, to connect with the bus conductor 26. The wire 20c extends in the x-direction through the ring cores 24/10, 23/6, 23/7, 23/8 and in the y-direction through the cores 24/9, 24/8, 24/7, as well as through the ring cores 23/9 and 23/B up to the conductor 26. The wire 20d extends in the x-direction through the ring cores 24/1, 24/4, 24/7, 23/D, 23/C and in the ydirection through the cores 23/6, 23/3, 23/0 to connect with the conductor 26. The wire 20e passes in the x-direction through the cores 24/2, 24/5, 24/8, 23/E and in the y-direction through the cores 23/D, 23/7, 23/4, 23/1 to the conductor 26. The wire 20f extends in the x-direction through the cores 24/3, 24/6, 24/9 and in the y-direction through the cores 23/E, 23/C, 23/8, 23/5, 23/2 to the conductor 26.

Each of the wires 20a to 20f, when energized, is traversed by a half-select current which is alone insufficient to switch one of finite memory cores from one to the other state of magnetic polarization. Hence the two wires in the x-and ydirections must be coincidently energized to cause magnetic switching of the one submatrix core with which the two wires are linked inductively. The same applies, generally, to the other core matrixes described hereinafter. The readout or sense windings 33 of the respective ring cores. only one such winding being shown, are connected by respective leads 34 to a bus conductor 35 carrying a voltage of +U, volt. The outputs 36 of the windings 33 are connected to the respective bases of I of respective transistors remaining transistors primary windings being a +U, volt conductor 77 and has its output end PNP switching transistors 37/A to 37/E and 37/0 to 37/10 whose emitters are all connected to a zero-voltage bus 38. The collectors of the transistors are connected to respective leads 39/A to 39/E and 39/0 to 39/10 which are wired as follows.

The leads 39/A to 39/E serve to carry signals indicative of signs and commands start, printing) and extend to program control devices of conventional type (not shown). The lead 39/ 10 is connected in series with the primary winding of a pulse transformer 41 to the lead 39/0. The secondary winding of pulse transformer 41 is connected by a lead 42 to the base of a switching transistor 43 whose emitter is connected through a lead 44 to a zero-voltage conductor and whose collector is connected by a lead 45 to the input 46 of a bistable flip-flop 47. The second input 48 of flip-flop 47 is connected to the clock frequency.

. The first output 49 of flip-flop 47 is connected to the base of aftransistor 50 whose emitter is connected by a lead 51 to the zero-voltage conductor and .whose collector is connected to a lead 52. Lead 52 is connected through a resistor 53 and a further lead 54 with the excitation windings (inhibit lines) of the ring cores in submatrix 23, these excitation or inhibit windings (not shown) extending between lead 54 and a conductor having a voltage of U, volt. The inhibit windings are common to cores 23/0 to 23/9 but do not extend through the ring cores 23/A, 23/B, 23/C, 23/D and 23/E. The second output 55 of the bistable flip-flop 47 is connected to the base of a switching transistor 56. The emitter .of transistor-56 is connected to a zero-voltage conductor 57, the collector being connected through a lead 58 and a resistor W to a conductor 59. The nonillustrated inhibit windings of the ring cores in submatrix 24 are connected between conductor 59 and the -U, volt conductor just mentioned.

The leads 39/0 to 39/9 are connected through respective resistors W1 (FIG. 1) to input leads 40/0 to 40/9 of the adder matrix DA (FIGS. 3, 4) which are wired as follows.

The adder matrix DA is subdivided into submatrixes 60 and 61(diagonal subdivision D-D according to FIG. 4). The wire 40/0 (FIG. 4) extends in the x-direction through the ring cores 61/0, 60/1 to 60/9 and in the y-direction through core 61/0. The wire 40/1 extends in the x-direction through the cores 61/2, 60/3 to 60/10 and in the y-direction through cores 61/2 and 60/1. The wire 40/2 extends in the x-direction through cores 61/4, 60/5 to 60/ 11 and in the y-direction through cores 61/4, 60/3 and 60/2. The other wires 4,0/3 to 40/9 are analogously wired. The digit value assigned to the ring cores linked with the wires in the x-direction increases one unit from one core to the next in that direction, whereas the value assigned to the cores traversed by wires in the y-direction decreases by one unit from core to core.

As is apparent from FIG. 3 and FIG. 4, the cores 60 or 61 of equal assigned values and appertaining to the respective value units to 18, are connected by respective leads 62/0 to 62/ 18 to a bus conductor 63 (FIG. 3) carrying a voltage of +U volt; and the signal windings 64/0 to 64/18 of these equivalent cores (shown only for the cores 60/5 and 60/18) have their output ends 67/0 to 67/18 connected to the bases 68 (FIG.

69/0 to 69/18 (FIGS. 3, 5).

The emitters of transistors 69/0 to 69/ 18 are in connection with a zero-voltage bus, and the collectors 71 of these transistors are connected with respective leads 72/0 to 72/9 (FIGS. 3, 1); and the collectors 71 of the respective ten transistors 69/0 to 69/9 are connected with leads 72/0 to 72/9 (FIGS. 1, 3). In contrast thereto, the collectors 71 of the 69/10 to 69/18 of this group are connected to the primary windings 73/10 to 73/18 of a transformer 74, the output leads 75/10 to 75/18 of the respective connected to leads 72/0 to 72/8. The secondary winding 76 of transformer 74 is in connection with attached to the base of a transistor 78 whose emitter lead 79 is connected to zero volt and whose collector is attached to the input lead 46 The leads 40/0 to 40/9, after having passed through the submatrix 60 or 61, terminate in a bus 80 (FIGS. 1. 3. 6) which is inductively linked with a ring core 81 (FIG. 6) and attached to a conductor 82 carrying a voltage of U, volt. Another conductor 83 of the same -U, voltage is-also linked with core 81 and is connected to the base of an NPN transistor 84 whose emitter is connected through a lead 85 to a voltage of U,, volt and whose collector is in connection with a wire 86. The wire 86 constitutes a signal winding which extends through the diagonally arranged cores 61/0, 61/2, 61/4 ....61/18 (FIGS. 1, 3, 6) to a zero-voltage lead 87.

The leads 72/0 to 72/9 extend to the above-mentioned code converter CW which is designed as a diode matrix of known type and has its outputs 90a to 90f attached to the respective bases of transistors 91a to 91f appertaining to the driver stage T (FIGS. 1, 3). The emitters of transistors 91a to 91f are connected to a zero-volt conductor 92 and their collector leads 93a to 93f are connected through respective resistors W2 with the wires 94a to 94f (FIGS. 1,- 7) which pass horizontally through the ring cores 95 of the accumulator AK and are attached to a bus 96 to which a voltage of -U, volt is applied. Respective wires 97/1'to 97/30traverse the cores 95 in the vertical direction, coming from the selector network AS.

The wires 94a to 94f are further connected to a read-out amplifier LV of any suitable conventional type, this amplifier being indicated diagrammatically in FIG. I. The output leads 98a to 98f of amplifier LV extend to the above-mentioned two-position selector W under control by a gating network T0 of any suitable configuration which is controllable by operation of a switch S. For example, the selector network W can be set by the above-mentioned accounting machine, data storer or program controller in such a manner that the computed values are transferred either through the leads 99 to the data processing devices of the accounting machine or to the memory of the programming controller, or that they are transferred through the leads 100 to the above-mentioned input conductors 20a to;20f.

From the wires 98a to 98f there extend respective branch leads 101a to l01fto the complements decoder KE (FIG. 8) which is also composed of two submatrixes 102, 103. The wire 101a passes in the y-direction (vertically) through the ring cores 103/9, 103/8, 103/7 and in the x-direction (horizontally) through cores 102/2, 102/1, 102/0 and is attached to the wire 104. The wire 101b extends through cores 103/0, 103/6, 103/5, 103/4 in the y-direction and through cores 102/5, 102/4, 102/3, 102/9 in the x-direction. also up to the wire I04. The wire 101c first extends in the y-direction through the ring cores 102/9, 103/3, 103/2, 103/1 and in the x-direction through the ring cores 102/8, 102/7, 102/6, 103/0. The wire 101d passes vertically'through cores 102/0, 102/3, 102/6 and horizontally through cores 103/3, 103/6, 103/9. The wire 101e extends vertically through cores 102/1, 102/4, 102/7 and horizontally through cores 103/2, 103/5 and 103/8 to the wire 104. The wire 101f extends vertically through cores 102/2, 102/5, 102/8 and horizontally through cores 103/1, 103/4 and 103/7, likewise to the wire 104.

The wire 104 is attached to the collector of a transistor 105 whose base 106 receives the lock frequency and whose emitter is connected through a lead 107 to a voltage of -U,, volt.

The submatrixes 102 and 103 have respective preexcitation or inhibit windings represented in FIG. 1 and 8 only by arrows at 108 and 109 respectively. The inhibit windings are connected in series. They may be constituted by a single inhibit line passing through all of the submatrix cores. The inhibit windings 108 are energized by counteracting current in the event of complement formation. This inhibiting current is supplied under control by the program controller (not illustrated). The inhibit windings 109 in submatrix 103, however, receive current from the programmer in the event of noncomplementation. The ring cores 0 to 9 assigned to the same decimal digit places are connected through schematically represented read-out windings 110/0 to 110/9 respectively with the bases of respective transistors 111/0 to 111/9 whose emitters are connected to zero volt and whose collectors are individually connected to leads 112/0 to 112/9 attached to the above-mentioned leads 39/0 to 39/9 respectively.

As mentioned, the accumulator AK is controlled with the 5 aid of the selector network AS (FIGS. 1, 7). This network is constituted by a ring core matrix 115 whose cores are selected by ring counters 116, 117 which are clock-pulse synchronized in known manner. The ring counter 116 counts each time up to 5, and the ring counter 117 up to 6. Accordingly, the five outputs 118/1 to 118/5 extending in the horizontal direction and the six outputs 119/1 to 119/6 in the vertical direction are passed through the ring cores of the matrix 115 to terminate in a bus 120 connected to the emitter of a transistor 121 having mentioned, the current intensity of the pulses is so rated that the coincident two pulses (half-select current) will reverse the magnetic polarization of a ringcore. By means of further series-connected windings (not illustrated) each ring core may be suitably premagnetized or biased for calibration of the magnetic switching operation.

The electronic computer so far described is capable of processing multidigital numbers (or other a-numerical words), preferably represented in the code (3), by a seriesparallel mode of operation, that is, digit by digit or bit by bit, beginning with the lowest decimal value position. During such operation the transfer of the number to be processed is effected on the same leads a to f as the retransfer of the computed results. The computer permits the performance of addition and subtraction, the subtraction being effected by addi- 40 tion of complementary values. Multiplication is effected by continued addition, and division by continued subtraction.

The processing of a digit or bit takes place in two phases within a clock-pulse period. In the first phase, the leads a to f transfer-from the input (such as the accounting machine or 5 memory) through the two-position selector W to the decoder CE-a numeral or digit value of one of the terms of the sum to be formed. Simultaneously a numeral or digit value is read out of the accumulator AK under control by the two ring counters 116, 117 and the selector network AS; and this read-out numeral is transferred through the read-out amplifier LV to the complements decoder KE.

While this is taking place, a particular one magnet core becomes reversely magnetized in one of the two submatrixes 5 5 manner. This causes an output signal to be issued to the cor- 65 responding transistors 37 and 111 with the effect that an output pulse is also transferred to the corresponding ones of leads 39/0 to 39/9 and 112/0 to 112/9.

The matrix wires assigned to a given value are connected with one another and through the respective resistors W1 and 70 respective conductors 40/0 to 40/9 to the adder matrix DA. This provides for two possibilities of data transfer to the adder:

1. When the output values from transfer decoder KB and from complements decoder CE differ from each other, 75

two selected ones of the leads /0 to 40/9 will carry currents simultaneously.

2. When the output values from decoder KE and the decoder CE are the same, only a single one of the respective conductors 40/0 to 40/9 will carry current.

In accordance with these two possibilities, the adder matrix DA is subdivided into two action regions (FIG. 3). When two inputs carry current, for example, the inputs 40/5 and 40/6 0 (for the numerals 5 and 6 respectively), there result three intersection points within the adder matrix DA, namely the two intersection points of the wires 40/5 and 40/6 (FIG. 4) each with itself, and the intersection (/11) of wire 40/5 with the wire 40/6. This establishes a coincidence condition for the ring cores 61/10, 60/11 and 61/12 located at these three intersection points because, as mentioned, the cores, having a substantially rectangular hysteresis loop, are so rated that a reversal in magnetic polarization can occur only when two mutually additive currents are present simultaneously. The ring cores 61/0, 61/2, 61/18, arranged on the diagonal D-D, are counterbiased (inhibited) by the inhibit windings 86 and 87, namely due to the face that the transistor 84 can be turned on by the ring core 81. This takes place when two inputs 40/0 to 40/9 carry current, whereby the two currents become added to each other in the bus 80 so that a current of double magnitude will flow through the magnet core 81, thus reversely magnetizing this core and thereby switching the transistor 84 to its on condition.

When only one of the respective leads 40/0 to 40/9 carries current, then only one of the cores 61/0, 61/2 to 61/18, is reversely magnetized, namely the one located on the diagonal D-D and at the intersection point of the one current-carrying wire with itself. Simultaneously, the ring core 81 is subjected only to a single half-select current pulse whose intensity is insufficient for reverse magnetization. Hence the ring cores on the diagonal D-D are not inhibited but in condition to be reversely magnetized.

Simultaneously with the reversal in magnetization of a core 60 or 61 in adder matrix DA, a signal is issued through the proper conductor 76/0 to 67/18 to one issued the respective transistors 69/9 to 69/18. This one transistor is turned on so that its output 72/0 to 72/9 or /10 to 75/18 will carry current. The selection of the particular transistors 69/0 to 69/18 corresponds to the result of the numerals to be added. If the result is equal to, or larger than 10, this result must be split into a unit decimal and a tens decimal. In the present example: 5 l- 6 11, the transistor 69/11 will be turned on and the appertaining primary winding 73/11 will be energized so that the pulse transformer 74 causes the transistor 78 to be turned on with the effect of setting the bistable flip-flop 47 through lead 46. In this manner, a tens transfer for the next decimal place is stored. Simultaneously, the lead 75/11 is connected with the lead 72/1 through which the value of the unit place 1 is issued to the code converter CW.

The bistable flip-flop 47 connected to the clock-frequency line, is kept in the zero state unless a transfer pulse reaches the second input of the flip-flop through lead 46 or lead 45. In the latter case, the flip-flop 47 remains in the I state until the end of the first phase of the next following clock-pulse period. In the zero state of the bistable flip-flop 47 the ring cores of the submatrix 24 are counterbiased (inhibited) so that no core of this half-matrix can be reversely magnetized. The cores of submatrix 23, however, are not inhibited and can be to magnetized, namely so that the respective states of magnetization of cores 23/0 to 23/9 represent the decoded numerals in the (2) code.

The core 23/0 is situated at the intersection of wire 20a with wire 2011 (FIG. 9). Since the bistable flip-flop 47, due to the transfer pulse on conductor 46, has been triggered to the I state, the cores of submatrix 26 are inhibited and the cores of submatrix 24 are released. The cores 24/1 to 24/10 represent the decoded numerals of the (2) code increased by one unit.

Thus the tens transfer is taken into account when the next numeral arrives.

The ring cores 23/A to 23/E are not affected by the inhibiting bias magnetization. They are always in ready condition and serve for the transmission of five possible additional characters or commands. The two submatrixes 102 and 103' of the complements decoder KE are arranged in analogy to the submatrixes 23 and 24 of the transfer decoder The submatrix 102 represents the decoded values of the (3) code, and the submatrix 103 represents the nine complement of the (3) code. Depending upon the course of the computer program, decoder Ke provides an inhibiting premagnetization of the cores either in submatrix 102 or in submatrix 103, depending upon whether the computer is to perform an adding or subtracting operation. The program controller may be of any suitable known type and may operate with a fixed or an adjustable or selective program.

In the code converter CW the arriving decimal values are again coded and entered through the driver T into the accumulator AK in the form of writing current. These writing currents, occurring during the second phase of the clock-pulse period, can set corresponding magnet cores in the same column from which previously the numeral was readout during the first phase. The selection of the columns takes place in known manner through the ring cores 115 of'the selector net'- work AS. The driver currents for these ring cores are taken from the ring counters 116 and 117 which are simultaneously controlled by clock pulses and which operate cyclically as ring-shift counters. The 30 positions of the accumulator AK are selected by virtue of the fact that the ring counter 116 performs five cycles and the ring counter 117 six cycles.

The result stored in the accumulator AK can be supplied to the accounting machine or to another memory or other desired device, in series operation, that is column by column, by means of the program-control device and the ring counters 116, 117 through the leads 94a to 94f and 98a to 98f and through the gate network To and the selector switch unit W.

To those skilled in the art it will be obvious upon a study of this disclosure, that my invention permits of various modifications with respect to the number and design of individual system components, as well as their interwiring or system grouping, and relative to the particular a-numerical or digital word configurations and code combinations to be employed, and hence may be given embodiments other than particularly illustrated and described herein, without departing from the essential features of my invention and within the scope of the.

claims annexed hereto.

Iclaim: 1. An electronic computer for the series-parallel processing of digital numbers, comprising:

ring core matrix circuits having ring cores and line and column circuits for selecting the ring cores, each of said line circuits being connected in series with a corresponding one of said column circuits; an adder matrix (DA) including said ring core matrix circuits and having two submatrixes (60, 61); and a decoder matrix having two decodermat'rixes (CE, KE) for decoding and for the input of the digitalnumbers processed in pairs, each of said decoder matrixes having two submatrixes said decoder matrixes having output leads for providing an output indication of a computation result, said output leads'providing inputs to the ring cores of said adder matrix, each of the ring cores of one of said submatrixes said adder matrix being provided at the intersection of an output lead with itself and being set in accordance with an output lead having potential thereon, wherein when there is a potential on two of said output leads at a ring core said ring core is set and simultaneous excitation of the ring cores at the other intersections is ineffectuated by counter-excitation. 2. In a computer according to claim 1, said decoder mat rix having ring cores, which have write-in wires extending through each core of said two decoder submatrixes in the line (x) direction and column (y) direction respectively of the matrix.

3. In a computer according to claim 1, saiddecoder matrix (CE) for decoding of serially entereddecimal digits having means for tens transfer of the previously processed decimal digit, said tens transfer means being constituted by one of said two submatrixes of said decoder.

4. A computer according to claim 1, comprising a complement decoder matrix (KE) to which said adder matrix is connected, wherein one of said decoder matrixes comprises two submatrixes (102, 103') with'write-in wires and read-out wires and having respective inhibit lines (108, 109) inductively linked with the coresof' said two submatrixes respectively for selectively controlling one of said respectivesubmatrixes' to be active at a time so as to transfer to said adder matrix (DA) the decoded decimal digits from one of said submatrixes for adding operation and to transfer to said adder matrix the decoded nine-complementsfofv said digits from said other submatrix for subtracting operation.

5. In a computer according to claim 4, said decoder matrixes having each of said ring cores inductively linked with a pair of different ones of said'write-in wires so as to require coincident current flow in both wires for reversal of magnetization, said adder matrix having the cores of one of its submatrixes inductively linked with apair of different write-in wires and having the cores ofi ts other submatrix inductively linked twice with-a single one ofthe respective write-in wires v trolled means for readout of said values from said accumulator in a first phase of a clock-pulse period, said read-out means being connected to said write-in wiresof readout decoder matrix for intermediate storing of the readout value in said decoder matrix, said two decoder matrixes having their respective read-out wires connected to said adder matrix, and code converter meansconnected between the readout wires of said adder matrix and the input of said accumulator, whereby the adder matrix in a second phase of the clock-pulse period computes a result from data supplied by said two 8. A memory matrix of magnetic memory cores having write-in wires inductively linked with the'cores for writing digital data into the matrix and having read-out wires also linked with said cores, said matrix being composed of two submatrixes, each of the cores in one of said two submatrixes (60) being inductively liriked'with a different pair of said write-in wires (40/0 to 40/9) for coincident response to respective half-select currents flowing in the two wires'of said pair, said other matrixes (61) having'each of its cores inductively linked at least twice with a single one of said respective write-in wires (40/0 to 40/9) for cumulative response to' at least twice the half-select current flowing in said one wire, and eachof said read-out wires being linked with the respective cores of equal assigned digital values in each of said two submatrixes.

9. In a matrix according to claim 8, each of said pairs of write-in wires extending in the line direction and column direction respectively through each of saidcores of said one matrix, and each of said single write-in wires extending in said two directions through each of saidcores of said other submatrix.

I ill. iii"; matrix according to claim 9, said cores of said other submatrix having an inhibit 'line in common, and' control means connected with said inhibit line for selectively readying and inhibiting said other submatrix.

was read out in the first'phase'of said 11. A decoder matrix of magnetic ring cores for decoding of serially entered decimal numbers, having write-in wires inductively linked with the matrix cores for writing digital data into the matrix and having read-out wires also linked with said cores, said matrix comprising two submatrixes. each of said write-in wires being inductively linked with respective cores in both said submatrixes, each of said read-out wires being linked with the respective cores of equal assigned digital values in each of said two submatrixes, an inhibit line inductively linked with the cores of one of said submatrixes, and control means connected with said inhibit line for selectively readying and inhibiting said submatrix.

12. An electronic computer for the series-parallel processing of digital numbers, comprising:

at least one decoder matrix (CE, KB) of magnetic memory cores having write-in wires inductively linked with the matrix cores for writing the digital numbers into said matrix and having read-out wires also linked with said cores; an adder matrix (DA) of magnetic memory cores having write-in wires, means for supplying current to said latter write-in wires in accordance with flow of current in said respective readout wires of said decoder matrix, output conductors linked with the adder-matrix cores for furnishing an output indicative of a computation result; and each of said decoder and adder matrixes being divided into two submatrixes (23, 24; 102, 103; 60, 61) and the writein wires (4 to for 40/0 to 40/9) of each matrix extending through respective cores of its two submatrixes, said adder matrix having each of the cores in one of its two submatrixes (60) inductively linked with a different pair of said write-in wires (40/0 to 40/9) for coincident response to respective half-select currents flowing in the two wires of said pair, said other submatrix (61) of said adder matrix having each of its cores inductively linked at least twice with a single one of said respective write-in wires (40/0 to 40/9) for cumulative response to at least twice the half-select current flowing in said one wire. 13. An electronic computer for the series-parallel processing of digital numbers, comprising:

at least one decoder matrix (CE, KB) of magnetic memory cores having write-in wires inductively linked with the matrix cores for writing the digital numbers into said matrix and having read-out wires also linked with said cores;

an adder matrix (DA) of magnetic memory cores having write-in wires, means for supplying current to said latter write-in wires in accordance with flow of current in said respective read-out wires of said decoder matrix, output conductors linked with the adder-matrix cores for furnishing an output indicative of a computation result;

each of said decoder and adder matrixes being divided into two submatrixes (23, 24; 102, 103; 60, 61) and the writein wires (a to f or 40/0 to 40/9) of each matrix extending through respective cores of its two submatrixes;

a complement decoder matrix (KE) to which said adder matrix is connected, said complement decoder matrix being composed of two submatrixes (102, 103) with write-in wires and read-out wires and having respective inhibit lines (108, 109) inductively linked with the cores of said two submatrixes respectively for selectively controlling one of said respective submatrixes to be active at a time so as to transfer to said adder matrix (DA) the decoded decimal digits from one of said submatrixes for adding operation and to transfer to said adder matrix the decoded nine-complements of said digits from said other submatrix for subtracting operation.

14. In a computer according to claim 13, said decoder matrixes having each of said ring cores inductively linked with a pair of different ones of said write-in wires so as to require coincident current flow in both wires for reversal of magnetization, said adder matrix having the cores of one of its submatrixes inductively linked with a pair of different write-in wires and having the cores of its other submatrix inductively linked twice with a single one of the respective write-in wires whereby the latter cores are reversely magnetized by current in said single wire.

15. in a computer according to claim 14, said two decoder matrixes forming intermediate memories for the digital values decoded therein.

16. A computer according to claim 15, comprising a data accumulator (AK) for storing of digit values, clock-pulse controlled means for readout of said values from said accumulator in a first phase of a clock-pulse period, said readout means being connected to said write-in wires of said complement decoder matrix for intermediate storing of the readout value in said complement decoder matrix, said two decoder matrixes having their respective readout wires connected to said adder matrix, and code converter means connected between the readout wires of said adder matrix and the input of said accumulator, whereby the adder matrix in a second phase of the clock-pulse period computes a result from data supplied by said two decoder matrixes and passes said result through said code converter into the same storage place of said accumulator from which a digit value was read out in the first phase of said period. 

1. An electronic computer for the series-parallel processing of digital numbers, comprising: ring core matrix circuits having ring cores and line and column circuits for selecting the ring cores, each of said line circuits being connected in series with a corresponding one of said column circuits; an adder matrix (DA) including said ring core matrix circuits and having two submatrixes (60, 61); and a decoder matrix having two decoder matrixes (CE, KE) for decoding and for the input of the digital numbers processed in pairs, each of said decoder matrixes having two submatrixes said decoder matrixes having output leads for providing an output indication of a computation result, said output leads providing inputs to the ring cores of said adder matrix, each of the ring cores of one of said submatrixes said adder matrix being provided at the intersection of an output lead with itself and being set in accordance with an output lead having potential thereon, wherein when there is a potential on two of said output leads at a ring core said ring core is set and simultaneous excitation of the ring cores at the other intersections is ineffectuated by counter-excitation.
 2. In a computer according to claim 1, said decoder matrix having ring cores, which have write-in wires extending through each core of said two decoder submatrixes in the line (x) direction and column (y) direction respectively of the matrix.
 3. In a computer according to claim 1, said decoder matrix (CE) for decoding of serially entered decimal digits having means for tens transfer of the previously processed decimal digit, said tens transfer means being constituted by one of said two submatrixes of said decoder.
 4. A computer according to claim 1, comprising a complement decoder matrix (KE) to which said adder matrix is connected, wherein one of said decoder matrixes comprises two submatrixes (102, 103) with write-in wires and read-out wires and having respective inhibit lines (108, 109) inductively linked with the cores of said two submatrixes respectively for selectively controlling one of said respective submatrixes to be active at a time so as to transfer to said adder matrix (DA) the decoded decimal digits from one of said submatrixes for adding operation and to transfer to said adder matrix the decoded nine-complements of said digits from said other submatrix for subtracting operation.
 5. In a computer according to claim 4, said decoder matrixes having each of said ring cores inductively linked with a pair of different ones of said write-in wires so as to require coincident current flow in both wires for reversal of magnetization, said adder matrix having the cores of one of its submatrixes inductively linked with a pair of different write-in wires and having the cores of its other submatrix inductively linked twice with a single one of the respective write-in wires whereby the latter cores are reversely magnetized by current in said single wire.
 6. In a computer according to claim 5, said two decoder matrixes forming intermediate memories for the digital values decoded therein.
 7. A computer according to claim 6, comprising a data accumulator (AK) for storing of digit values, clock-pulse controlled means for readout of said values from said accumulator in a first phase of a clock-pulse period, said read-out means being connected to said write-in wires of readout decoder matrix for intermediate storing of the readout value in said decoder matrix, said two decoder matrixes having their respective read-out wires connected to said adder matrix, and code converter means connected between the readout wires of said adder matrix and the input of said accumulator, whereby the adder matrix in a second phase of the clock-pulse period computes a result from data supplied by said two decoder matrixes and passes said result through said code converter into the same storage place of said accumulator from which a digit value was read out in the first phase of said period.
 8. A memory matrix of magnetic memory cores having write-in wires inductively linked with the cores for writing digital data into the matrix and having read-out wires also linked with said cores, said matrix being composed of two submatrixes, each of the cores in one of said two submatrixes (60) being inductively linked with a different pair of said write-in wires (40/0 to 40/9) for coincident response to respective half-select currents flowing in the two wires of said pair, said other matrixes (61) having each of its cores inductively linked at least twice with a single one of said respective write-in wires (40/0 to 40/9) for cumulative response to at least twice the half-select current flowing in said one wire, and each of said read-out wires being linked with the respective cores of equal assigned digital values in each of said two submatrixes.
 9. In a matrix according to claim 8, each of said pairs of write-in wires extending in the line direction and column direction respectively through each of said cores of said one matrix, and each of said single write-in wires extending in said two directions through each of said cores of said other submatrix.
 10. In a matrix according to claim 9, said cores of said other submatrix having an inhibit line in common, and control means connected with said inhibit line for selectively readying and inhibiting said other submatrix.
 11. A decoder matrix of magnetic ring cores for decoding of serially entered decimal numbers, having write-in wires inductively linked with the matrix cores for writing digital data into the matrix and having read-out wires also linked with said cores, said matrix comprising two submatrixes, each of said write-in wires being inductively linked with respective cores in both said submatrixes, each of said read-out wires being linked with the respective cores of equal assigned digital values in each of said two submatrixes, an inhibit line inductiveLy linked with the cores of one of said submatrixes, and control means connected with said inhibit line for selectively readying and inhibiting said submatrix.
 12. An electronic computer for the series-parallel processing of digital numbers, comprising: at least one decoder matrix (CE, KE) of magnetic memory cores having write-in wires inductively linked with the matrix cores for writing the digital numbers into said matrix and having read-out wires also linked with said cores; an adder matrix (DA) of magnetic memory cores having write-in wires, means for supplying current to said latter write-in wires in accordance with flow of current in said respective readout wires of said decoder matrix, output conductors linked with the adder-matrix cores for furnishing an output indicative of a computation result; and each of said decoder and adder matrixes being divided into two submatrixes (23, 24; 102, 103; 60, 61) and the write-in wires (a to f or 40/0 to 40/9) of each matrix extending through respective cores of its two submatrixes, said adder matrix having each of the cores in one of its two submatrixes (60) inductively linked with a different pair of said write-in wires (40/0 to 40/9) for coincident response to respective half-select currents flowing in the two wires of said pair, said other submatrix (61) of said adder matrix having each of its cores inductively linked at least twice with a single one of said respective write-in wires (40/0 to 40/9) for cumulative response to at least twice the half-select current flowing in said one wire.
 13. An electronic computer for the series-parallel processing of digital numbers, comprising: at least one decoder matrix (CE, KE) of magnetic memory cores having write-in wires inductively linked with the matrix cores for writing the digital numbers into said matrix and having read-out wires also linked with said cores; an adder matrix (DA) of magnetic memory cores having write-in wires, means for supplying current to said latter write-in wires in accordance with flow of current in said respective read-out wires of said decoder matrix, output conductors linked with the adder-matrix cores for furnishing an output indicative of a computation result; each of said decoder and adder matrixes being divided into two submatrixes (23, 24; 102, 103; 60, 61) and the write-in wires (a to f or 40/0 to 40/9) of each matrix extending through respective cores of its two submatrixes; a complement decoder matrix (KE) to which said adder matrix is connected, said complement decoder matrix being composed of two submatrixes (102, 103) with write-in wires and read-out wires and having respective inhibit lines (108, 109) inductively linked with the cores of said two submatrixes respectively for selectively controlling one of said respective submatrixes to be active at a time so as to transfer to said adder matrix (DA) the decoded decimal digits from one of said submatrixes for adding operation and to transfer to said adder matrix the decoded nine-complements of said digits from said other submatrix for subtracting operation.
 14. In a computer according to claim 13, said decoder matrixes having each of said ring cores inductively linked with a pair of different ones of said write-in wires so as to require coincident current flow in both wires for reversal of magnetization, said adder matrix having the cores of one of its submatrixes inductively linked with a pair of different write-in wires and having the cores of its other submatrix inductively linked twice with a single one of the respective write-in wires whereby the latter cores are reversely magnetized by current in said single wire.
 15. In a computer according to claim 14, said two decoder matrixes forming intermediate memories for the digital values decoded therein.
 16. A computer according to claim 15, comprising a data accumulator (AK) for storing of digit values, clock-pulse controlled means for readout of said values from said accumulator in a first phase of a clock-pulse period, said readout means being connected to said write-in wires of said complement decoder matrix for intermediate storing of the readout value in said complement decoder matrix, said two decoder matrixes having their respective readout wires connected to said adder matrix, and code converter means connected between the readout wires of said adder matrix and the input of said accumulator, whereby the adder matrix in a second phase of the clock-pulse period computes a result from data supplied by said two decoder matrixes and passes said result through said code converter into the same storage place of said accumulator from which a digit value was read out in the first phase of said period. 